---
title: "ASIC Engineering Digital Designer/ Leader… – Pune, India"
canonical: "https://www.metaintro.com/job/asic-engineering-digital-designer-leader-digital-design-fsm-cpu-sub-e7b3c03e-6a9f-5ced-830e-2ec6efc017f3"
language: "en"
author: "Metaintro"
---

[/company/555-cisco-systems-international-b-v](/company/555-cisco-systems-international-b-v)[555 Cisco Systems International B.V.](/company/555-cisco-systems-international-b-v)
# ASIC Engineering Digital Designer/ Leader (digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune) at 555 Cisco Systems International B.V.

**Setup**
: On-site

**Location**
: Pune, Maharashtra

**Type**
: Full-time

**Level**
: senior

**Posted**
: May 21, 2026

## Description

Cisco’s Client Optics Group is hiring a Digital Design Lead to provide technical leadership for digital logic in silicon photonics and Co-Packaged Optics. The role owns the full ASIC/SoC lifecycle, including RTL design of CPU subsystems and data-path interfaces, verification, physical design, DFT, synthesis, timing closure, FPGA prototyping, and post-silicon validation. The position requires a bachelor’s or master’s degree in electrical or electronics engineering, 8–12 years of industry experience, and expertise in high-speed optical interconnects, SerDes, ASIC/SoC design flows, and cross-functional collaboration.

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