---
title: "ASIC Engineering Technical Leader… – Bengaluru, India"
canonical: "https://www.metaintro.com/job/asic-engineering-technical-leader-design-verification-verilog-system-e676e34d-dbf3-502d-9ef6-97423dc3c477"
language: "en"
author: "Metaintro"
---

[/company/555-cisco-systems-international-b-v](/company/555-cisco-systems-international-b-v)[555 Cisco Systems International B.V.](/company/555-cisco-systems-international-b-v)
# ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years at 555 Cisco Systems International B.V.

**Setup**
: On-site

**Location**
: Bengaluru, Karnataka

**Type**
: Full-time

**Level**
: lead/mgmt

**Posted**
: May 8, 2026

## Description

Cisco SiliconOne is hiring an ASIC Engineering Technical Leader to lead design verification for high-performance, high-volume ASICs. The role owns verification activities across RTL, emulation, pre-silicon, and post-silicon phases; develops and improves UVM/System Verilog testbenches, test plans, coverage, emulation infrastructure, and debugging workflows; coordinates with architecture, design, software, and other cross-functional teams; and leads and mentors junior engineers. The position requires a BS/MS and 12+/10+ years of hands-on ASIC design verification experience, along with expertise in System Verilog, UVM, C/C++, hardware emulation, and silicon validation.

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