---
title: "ASIC Implementation Engineer STA at broadcom – San Jose, CA"
canonical: "https://www.metaintro.com/job/asic-implementation-engineer-sta-at-broadcom-e0201894-3cc0-5de0-8099-ce7be24cda5c"
language: "en"
author: "Metaintro"
---

[/company/broadcom-4c962ebe](/company/broadcom-4c962ebe)[broadcom](/company/broadcom-4c962ebe)
# ASIC Implementation Engineer STA at broadcom

Compensation · Listed in posting

$143,800 – $230,000/yr

**Location**
: San Jose, California

**Type**
: Full-time

**Level**
: senior

**Posted**
: Sep 17, 2026

## Description

The Full Chip Static Timing Analysis (STA) Engineer owns final timing closure for ASIC designs, including PVT-corner sign-off, SDC constraint development, multi-mode multi-corner analysis, timing ECOs, and automation using Tcl, Python, and Perl. The role requires a bachelor’s degree in electrical or computer engineering, at least 12 years of ASIC STA and timing-closure experience, and expertise with Cadence or Synopsys tools. The annual base salary is USD 143,800 to USD 230,000, with discretionary bonus, equity, and medical, dental, and vision benefits.

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