---
title: "ASIC Verification Engineer at HPE – Sunnyvale, CA · Hybrid"
canonical: "https://www.metaintro.com/job/asic-verification-engineer-at-hpe-ed3c1e5c-9997-5b36-baef-e6f5539041a9"
language: "en"
author: "Metaintro"
---

[/company/hpe](/company/hpe)[HPE](/company/hpe)
# ASIC Verification Engineer at HPE

Compensation · Listed in posting

$120,000 – $243,000/yr

**Setup**
: Hybrid

**Location**
: Sunnyvale, California

**Type**
: Full-time

**Level**
: senior

**Posted**
: Aug 19, 2026

## Description

Hewlett Packard Enterprise is hiring an ASIC Verification Engineer for its networking silicon development team in Sunnyvale, California. The hybrid role requires working from an HPE office two days per week and involves owning block-level or subsystem verification, developing UVM environments, performing constraint-driven random testing, debugging complex SoC designs, and collaborating with cross-functional teams. Candidates need at least five years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with industry-standard simulation tools. The listed base salary range for California is USD 120,000 to 243,000 annually, with variable incentives possibly offered.

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