---
title: "CAD Developer, IR, Timing… at NVIDIA – Huangpu, China"
canonical: "https://www.metaintro.com/job/cad-developer-ir-timing-and-physical-design-optimization-at-nvidia-d2a05419-6c19-59b5-a90d-74d77d120993"
language: "en"
author: "Metaintro"
---

[![NVIDIA logo](/api/favicon-proxy?url=https%3A%2F%2Fnvidia.com%2Ffavicon.ico)](/company/nvidia)[NVIDIA](/company/nvidia)
# CAD Developer, IR, Timing and Physical Design Optimization at NVIDIA

Department: Engineer, ASIC

LanguageEnglish
中文

**Setup**
: On-site

**Location**
: Huangpu, Shanghai

**Type**
: Full-time

**Level**
: not_specified

**Posted**
: Aug 3, 2026

## Description

The ASIC-PD team is hiring junior and senior engineers to work on physical design from RTL through GDSII, including design quality checks, synthesis, formal checks, partitioning, constraints, async checks, timing analysis, and related flows. The role also involves inventing and optimizing chip-frequency and power-consumption methods, improving C++ algorithms for IR-drop optimization and simulation, and developing software used by design teams. Candidates need a BS, MS, or PhD in Electrical Engineering, Computer Science, or an equivalent field, at least two years of relevant CAD and VLSI hardware design experience, C++ software development ability, and knowledge of VLSI IR-drop concepts.

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