---
title: "Design Verification Engineer at Altera – Ringas, India"
canonical: "https://www.metaintro.com/job/design-verification-engineer-at-altera-60ef2abd-7931-53bb-bd84-79d4d7c60d30"
language: "en"
author: "Metaintro"
---

[/company/altera](/company/altera)[Altera](/company/altera)
# Design Verification Engineer at Altera

**Location**
: Ringas, Rajasthan

**Type**
: Full-time

**Level**
: mid

**Posted**
: Jul 29, 2026

## Description

Altera is hiring a Design Verification Engineer to design, develop, validate, and debug software abstractions and frameworks for FPGA acceleration supporting embedded, data center, and communication clients. The role focuses on UVM-based verification environments, SystemVerilog, testbenches, drivers, monitors, scoreboards, assertions, formal verification, simulation regression, coverage, and automation using Python or Perl. It requires a bachelor's or master's degree in a relevant engineering field and at least two years of ASIC or FPGA design verification experience, with a primary location of Regus, Madhapur and a Shift 1 schedule in India.

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