---
title: "Design Verification Engineer at Apple – Austin, TX +2"
canonical: "https://www.metaintro.com/job/design-verification-engineer-at-apple-2612dbcf-d8dc-51b0-8a06-d330dc9185ae"
language: "en"
author: "Metaintro"
---

[![Apple logo](/api/favicon-proxy?url=https%3A%2F%2Fwww.google.com%2Fs2%2Ffavicons%3Fdomain%3Dwww.apple.com%26sz%3D128)](/company/apple)[Apple](/company/apple)
# Design Verification Engineer at Apple

Department: Hardware

**Location**
: Austin, Texas · San Diego, California · +1

**Level**
: senior

**Posted**
: Jun 11, 2026

## Description

Apple is hiring a Design Verification Engineer to verify innovative, high-throughput cellular baseband modems and transceiver link controllers for its silicon products. The role focuses on creating reusable UVM verification environments, coverage-driven and directed test plans, RTL simulation bring-up through sign-off, regression maintenance, and the use of LLMs and Python-based automation to improve verification quality and productivity. Candidates need a bachelor's degree and at least 10 years of relevant industry experience, along with strong System Verilog, UVM, System C, C/C++, Python, and design verification expertise.

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