---
title: "Design Verification Engineer at Apple – Cupertino, CA"
canonical: "https://www.metaintro.com/job/design-verification-engineer-at-apple-79208f81-82ec-5d8a-9889-d52e5adf97f3"
language: "en"
author: "Metaintro"
---

[![Apple logo](/api/favicon-proxy?url=https%3A%2F%2Fwww.google.com%2Fs2%2Ffavicons%3Fdomain%3Dwww.apple.com%26sz%3D128)](/company/apple)[Apple](/company/apple)
# Design Verification Engineer at Apple

Department: Hardware

Compensation

$174,149 – $194,700/yr

**Location**
: Cupertino, California

**Type**
: Full-time

**Level**
: not_specified

**Posted**
: Oct 1, 2026

## Description

Apple is hiring a SoC Verification Engineer in Cupertino, California and other unanticipated locations throughout the United States. The role reviews design and architecture specifications, develops test plans, testbenches, and verification methodology, collaborates with design, architecture, and software teams, and runs and triages regressions while analyzing coverage. The position requires a master’s degree or foreign equivalent in Electrical and Computer Engineering, Electronics Engineering, or a related field, along with experience using System Verilog, Perl and Python, digital and computer architecture concepts, UVM, and functional coverage for SoC verification. It is a 40-hour-per-week role with a base-pay range of $174,149 to $194,700 per year.

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