---
title: "Design Verification Engineer at Apple – Cupertino, CA"
canonical: "https://www.metaintro.com/job/design-verification-engineer-at-apple-d36f9764-021d-5ea7-b6bb-78227604fa9e"
language: "en"
author: "Metaintro"
---

[![Apple logo](/api/favicon-proxy?url=https%3A%2F%2Fwww.google.com%2Fs2%2Ffavicons%3Fdomain%3Dwww.apple.com%26sz%3D128)](/company/apple)[Apple](/company/apple)
# Design Verification Engineer at Apple

Department: Hardware

Compensation

$174,149 – $225,300/yr

**Location**
: Cupertino, California

**Type**
: Full-time

**Level**
: not_specified

**Posted**
: Oct 1, 2026

## Description

Apple is hiring a System Verilog/UVM Verification Engineer in Cupertino, California and other unanticipated locations throughout the United States. The role designs and implements testbench environments and test cases, develops UVM-based System Verilog checkers, executes regression tests, analyzes failures, traces signals with Verdi, and collaborates with design and microarchitecture teams. It requires a master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field, along with experience in System Verilog, RTL modeling, UVM testbenches, randomized testing, computer architecture, and functional coverage. The role is 40 hours per week and offers a base-pay range of $174,149 to $225,300 per year, plus medical and dental coverage and other benefits.

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