---
title: "Design Verification Engineer — Memory… – California"
canonical: "https://www.metaintro.com/job/design-verification-engineer-memory-subsystem-at-qualcomm-715724dc-d104-53cb-a84c-c6bf22ff5820"
language: "en"
author: "Metaintro"
---

[/company/qualcomm-international-inc-mexico-branch-office](/company/qualcomm-international-inc-mexico-branch-office)[Qualcomm International Inc., Mexico Branch Office](/company/qualcomm-international-inc-mexico-branch-office)
# Design Verification Engineer — Memory Subsystem at Qualcomm International Inc., Mexico Branch Office

Department: ASICS Engineering

Compensation

$159,600 – $239,400/yr

**Setup**
: On-site

**Location**
: California

**Type**
: Full-time

**Level**
: mid

**Posted**
: Sep 17, 2026

## Description

Qualcomm is hiring a Design Verification Engineer for its memory subsystem verification team. The role covers the full verification lifecycle for complex digital designs, including memory controllers, DDR/LPDDR/HBM interfaces, PHY-related logic, and other high-performance memory subsystem components. Responsibilities include developing verification strategies and plans, building UVM-based testbenches, creating assertions and coverage models, executing simulations, debugging failures, and driving functional, code, assertion, and coverage closure. The position requires a bachelor’s, master’s, or PhD degree in a relevant technical field and 2–10 years of ASIC, SoC, IP, or subsystem design verification experience, with a pay range of $159,600 to $239,400.

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