---
title: "Digital Design Verification… at Altera – Iași, Romania"
canonical: "https://www.metaintro.com/job/digital-design-verification-engineer-at-altera-a7f952a4-8103-57e2-8c9d-4e0e5265da8f"
language: "en"
author: "Metaintro"
---

[/company/altera](/company/altera)[Altera](/company/altera)
# Digital Design Verification Engineer at Altera

LanguageEnglish
Română

**Setup**
: Remote

**Location**
: Iași

**Type**
: Full-time

**Level**
: entry

**Posted**
: Sep 28, 2026

## Description

Altera is hiring an FPGA Verification Engineer to develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks. The role involves writing testbenches, functional coverage models, and assertions; running simulations; debugging RTL and testbench issues; and collaborating with design, architecture, and analog teams. It is intended for an early-career engineer with 0–5 years of digital design or verification experience, a relevant bachelor's degree, and strong digital design fundamentals. The position is based in Iași, Romania and is remote.

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