---
title: "Digital Verification Senior… – Ho Chi Minh City, Vietnam"
canonical: "https://www.metaintro.com/job/digital-verification-senior-staff-engineer-at-synopsys-4db27016-e16a-57ce-90ea-05bb5cfb28ec"
language: "en"
author: "Metaintro"
---

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# Digital Verification Senior Staff Engineer at Synopsys

LanguageEnglish
Tiếng Việt

**Location**
: Ho Chi Minh City

**Level**
: senior

**Posted**
: Sep 4, 2026

## Description

Synopsys is hiring a senior mixed-signal PHY verification engineer to develop and execute verification plans, perform RTL and gate-level simulations, build functional tests, analyze power and waveforms, debug failures, and collaborate with design and integration teams on high-speed PHY IP. The role requires at least five years of ASIC RTL verification experience, strong SystemVerilog and UVM skills, SDF-annotated gate-level simulation expertise, and knowledge of power-analysis tools; DDR, HBM, or UCIe PHY knowledge is a plus. The position offers health, wellness, and financial benefits, with salary details provided by the recruiter.

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