---
title: "Lead Debug/Trace/Profiling… at SiFive – La Ciotat, France +3"
canonical: "https://www.metaintro.com/job/lead-debug-trace-profiling-design-engineer-at-sifive-a7dbdc2a-bd6f-544a-aaa9-b1bd7fba707c"
language: "en"
author: "Metaintro"
---

[![SiFive logo](/api/favicon-proxy?url=https%3A%2F%2Fwww.sifive.com%2Ffavicon.ico)](/company/sifive)[SiFive](/company/sifive)
# Lead Debug/Trace/Profiling Design Engineer at SiFive

LanguageEnglish
Français

**Location**
: La Ciotat, Provence-Alpes-Côte d'Azur · Cambridge, England · +2

**Type**
: Full-time

**Level**
: lead/mgmt

**Posted**
: Sep 30, 2026

## Description

SiFive is hiring a Hardware Design Technical Lead to architect, design, implement, and enhance debug, trace, and profiling hardware for RISC-V processor subsystems. The role involves RTL generator development, Chisel/FIRRTL integration, verification, documentation, and collaboration with architecture, performance, software, hardware, customer, partner, and tools-vendor teams. Candidates need substantial experience in debug/trace/profiling hardware, RTL design, CPU and SoC concepts, and a relevant MS or PhD.

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