---
title: "PERC Rule Deck Development… at Intel – Bengaluru, India"
canonical: "https://www.metaintro.com/job/perc-rule-deck-development-engineer-at-intel-f5a75ec7-d729-5290-9b3c-b2ef0ced816c"
language: "en"
author: "Metaintro"
---

[/company/intel](/company/intel)[Intel](/company/intel)
# PERC Rule Deck Development Engineer at Intel

**Location**
: Bengaluru, Karnataka

**Type**
: Full-time

**Level**
: senior

**Posted**
: Aug 26, 2026

## Description

Intel is hiring a PERC Runset Development Engineer in Bangalore, India, to develop, validate, and maintain PERC rule decks for electrical reliability verification. The role involves integrating verification flows across Calibre PERC, Cadence Pegasus, and Synopsys tools; collaborating with device physicists, process integration engineers, and analog designers; debugging reliability violations; automating checks with Python, SKILL, Tcl, or Perl; and documenting reliability check-sets. The position requires on-site presence and offers consideration for applicants with relevant electrical, computer, electronics, or semiconductor engineering experience.

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