---
title: "Physical Design and Full-Chip… at Intel – Hillsboro, OR +2"
canonical: "https://www.metaintro.com/job/physical-design-and-full-chip-soc-integration-engineer-at-intel-6c8a18cd-15cc-5373-86ba-634f3cda9c0b"
language: "en"
author: "Metaintro"
---

[/company/intel](/company/intel)[Intel](/company/intel)
# Physical Design and Full-Chip SoC Integration Engineer at Intel

Compensation

$141,910 – $200,340/yr

**Setup**
: Hybrid

**Location**
: Hillsboro, Oregon · California · +1

**Type**
: Full-time

**Level**
: senior

## Description

Intel Foundry is hiring an experienced Physical Design and Full-Chip SoC Integration Engineer for its Design Technology Platform organization in Hillsboro, Oregon, with additional locations in Santa Clara, California, and Austin, Texas. The role develops physical design methodologies and integrates hierarchical SoC layouts for advanced-node testchip vehicles, including floorplanning, layout verification and debugging, tape-in preparation, design-rule and constraint management, and coordination with process, yield, manufacturing, PDK, tool, and vendor teams. A master's degree in electrical engineering or a related field and at least five years of relevant experience are required. The position is hybrid and offers an annual US salary range of $141,910 to $200,340.

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