---
title: "Senior Debug Verification Engineer at Altera – San Jose, CA"
canonical: "https://www.metaintro.com/job/senior-debug-verification-engineer-at-altera-a71418dc-cdeb-5f1e-b175-2c3a7988498a"
language: "en"
author: "Metaintro"
---

[/company/altera](/company/altera)[Altera](/company/altera)
# Senior Debug Verification Engineer at Altera

Compensation

$149,100 – $215,000/yr

**Location**
: San Jose, California

**Type**
: Full-time

**Level**
: senior

**Posted**
: Sep 29, 2026

## Description

Altera is hiring a Sr. Debug Design Verification Engineer in San Jose, California, to perform pre-silicon SoC, FPGA, and full-chip design verification, including UVM testbench creation, verification strategy and test-plan development, and cross-functional coordination with design, software, and architecture teams. The role requires at least eight years of experience with complex ASIC designs or verification, SystemVerilog, UVM, and formal verification, with additional experience in JTAG, high-speed USB, PCIe, ARM, RISC, emulation, and UltraSoC/Tessent Embedded Analytics Debug Architecture preferred or advantageous. The regular shift is Shift 1 in the United States, with a Bay Area salary range of $149,100 to $215,000 USD.

## Trending job searches

Every query opens live roles, salary samples, and market demand — tap a search to run it instantly.

- [Find Senior Debug Verification Engineer jobs in San Jose, California, United States](/jobs/search?q=Find+Senior+Debug+Verification+Engineer+jobs+in+San+Jose%2C+California%2C+United+States)
- [Find roles similar to Senior Debug Verification Engineer in San Jose, California, United States](/jobs/search?q=Find+roles+similar+to+Senior+Debug+Verification+Engineer+in+San+Jose%2C+California%2C+United+States)
- [Find remote Senior Debug Verification Engineer jobs](/jobs/search?q=Find+remote+Senior+Debug+Verification+Engineer+jobs)
- [Find Senior Debug Verification Engineer jobs with UVM methodology and SystemVerilog](/jobs/search?q=Find+Senior+Debug+Verification+Engineer+jobs+with+UVM+methodology+and+SystemVerilog)
- [Find jobs similar to Senior Debug Verification Engineer](/jobs/search?q=Find+jobs+similar+to+Senior+Debug+Verification+Engineer)
- [Find Senior Debug Verification Engineer jobs posted this week](/jobs/search?q=Find+Senior+Debug+Verification+Engineer+jobs+posted+this+week)
- [Find Senior Debug Verification Engineer jobs paying $140,000 or more per year](/jobs/search?q=Find+Senior+Debug+Verification+Engineer+jobs+paying+%24140%2C000+or+more+per+year)
- [Find Science, Technology, Engineering, and Math jobs in San Jose, California, United States](/jobs/search?q=Find+Science%2C+Technology%2C+Engineering%2C+and+Math+jobs+in+San+Jose%2C+California%2C+United+States)

## Get More from Metaintro

Unlock powerful job search, personalized recommendations, and deep career insights from comprehensive, market-leading data and live market signals.

- [Browse all jobs](/jobs/search)
- [Access help center](/help)
- [Explore our content](/blog)

![](https://cdn.metaintro.com/rs:fill:1200:800/q:30/plain/images/bridges/bridge-expand.1df895c6bd76d96f.png)

For job seekers

## Ready to find a role that actually fits?

Upload your résumé, start a Job Search Thread, and let Metaintro rank real openings against your experience — then guide you from search to offer.

[Get Started Free](/signup)[Search matching jobs](/jobs/search)

Match

Compare live roles against your current evidence.

Position

Turn proof projects into role-specific applications.

Improve

Use market feedback to keep the skill plan current.

[Return to navigation](#main-navigation)