Qualcomm International Inc., Mexico Branch Office

3D Memory Chip Architect and Design, Principal Engineer at Qualcomm International Inc., Mexico Branch Office

Department: ASICS Engineering

Compensation

$200,000 – $300,000/yr

Setup: On-site
Location: San Diego, California
Type: Full-time
Level: senior
Posted: Sep 17, 2026

Description

Qualcomm is hiring a 3D Memory Architect to assess and optimize 3D DRAM and FLASH architectures for memory-centric compute systems serving data center, mobile, compute, and XR applications. The role focuses on near-memory computing organization, high-bandwidth data fabrics, power distribution, performance, power, and yield modeling, 3D chip floorplanning, and integration across memory, compute, packaging, and SoC teams. Candidates need a bachelor's, master's, or PhD in a science, engineering, or related field plus 6–8 years of ASIC design, verification, validation, integration, or related experience, with strong knowledge of memory architectures, buses, advanced packaging, and 3D integration. The disclosed pay range is $200,000 to $300,000.

Required Skills

3D Memory Design
3D Integration
Power Distribution
Verilog Modeling
EDA Tools
Matlab
Python
DRAM/FLASH Architecture

Additional Information

Minimum Education: Bachelor's degree in Science, Engineering, or a related field
Required Previous Experiences: 8+ years of ASIC design, verification, validation, integration, or related work experience
7+ years of ASIC design, verification, validation, integration, or related work experience
6+ years of ASIC design, verification, validation, integration, or related work experience
Preferred Qualifications: RTL, circuit, and system design experience for dataflow modeling and optimization
SoC architecture and power, clock, and bus design experience
DRAM/FLASH architecture performance assessment experience
Memory circuit design experience
Strong Verilog/Verilog-A/Verilog-AMS modeling ability
Familiarity with DRAM/FLASH datasheets and IO interfaces
ASIC, mixed-signal, and performance modeling experience
Knowledge of memory architecture, buses, and 2.5D/3D integration
Proficiency with EDA tools, Matlab, and Python
Master's or PhD in Electrical Engineering, Computer Science, or a related field