Description
The Lead Chip Packaging Design and Simulation Engineer will own packaging architecture and simulation from product definition through volume production, coordinating silicon, memory, board, cooling, foundry, assembly, test, substrate and supplier teams. Responsibilities include chip–package–board co-design, signal and power integrity, thermal and thermomechanical analysis, simulation-to-measurement validation, prototype testing, yield improvement, design signoff, and management of packaging design and simulation engineers. The role requires a bachelor’s degree or above in a relevant engineering field, at least 10 years of chip packaging design or development experience, and hands-on expertise in advanced packaging, interconnects, power delivery, cooling, reliability, and EDA or simulation tools.
