Description
The role leads process development and technical support for wafer bumping and/or fan-out processes used in silicon photonic chip manufacturing. Responsibilities include designing and optimizing early-stage process flows, qualifying materials, conducting reliability and stress testing, performing failure analysis, improving bumping parameters and yield, managing wafer quality control and SPC, and supporting NPI and process documentation. The position requires a bachelor's or master's degree in a relevant technical discipline and at least five years of hands-on wafer bumping or fan-out process integration or development experience at an OSAT or IDM advanced packaging line.
