Principal Engineer, Automated Derivatives at RenesasElectronics

Seniority in posting: director

Setup: Hybrid
Location: Austin, Texas
Type: Full-time
Level: senior
Posted: Aug 13, 2026

Description

The role leads end-to-end delivery of derivative SoCs across RTL design, functional verification, and physical implementation, using machine learning to predict physical outcomes, automate design variants, scale verification, prioritize regression, identify bug-prone modules, generate floorplan constraints, and reuse placement and routing solutions. It requires a master’s degree in a relevant engineering field, 12–15 years of semiconductor experience, and expertise in SystemVerilog, UVM, physical design, Python, Tcl, Git, and CI/CD.

Required Skills

SystemVerilog
UVM
Python
Tcl/Python
Git
CI/CD
STA
P&R

Additional Information

Minimum Education: Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering
Required Previous Experiences: 12–15 years of professional experience in the semiconductor industry
Proficiency in SystemVerilog for RTL design and UVM for functional verification
Understanding of synthesis, physical design, and static timing analysis
Expert Python skills for building and deploying models interfacing with simulation and implementation tools
Experience using Tcl/Python to extract features from simulation and implementation reports for predictive modeling
Mastery of Git and CI/CD pipelines for deploying design derivatives
Translation Company Name: Renesas Electronics