Description
STMicroelectronics is hiring an AMS Verification Engineer to develop and validate behavioral models and System Verilog real-number models for mixed-signal ASICs. The role involves configuring mixed-signal simulation environments, executing simulations, analyzing results, validating outcomes with analog and digital design teams, documenting technical findings, and improving verification methodologies. The position requires a master’s degree in electrical, electronic, or computer engineering, strong system-architecture understanding, programming and analytical skills, and familiarity with mixed-signal simulation platforms; experience with System Verilog real-number modeling is highly valued. The expected gross annual salary is €37,500–€42,000 RAL plus variable pay.
