Description
Synopsys is hiring an Analog I/O Sr Design Engineer to develop and qualify ESD and Latch-Up robust solutions for advanced interface IPs using FinFet, FDSOI, and BCD processes. The role owns the full lifecycle from schematic design and simulation through layout, silicon qualification, and production release; leads I/O ring design and optimization; develops interface testchips; runs ESD simulations; and collaborates with foundry and design teams. The engineer will improve reliability and performance of interface IPs and reduce field failures for global semiconductor customers.
