Analog Layout Automation Engineer at Apple

Department: Hardware

Compensation · Listed in posting

$166,600 – $296,000

Location: San Diego, California
Level: senior
Posted: Apr 20, 2026

Description

Apple is hiring an Analog Layout Automation Engineer to convert analog and mixed-signal circuit concepts into silicon for next-generation systems-on-chip. The role involves creating high-performance layouts, reviewing floor plans, analyzing circuits, running verification suites, resolving LVS/DRC/ERC issues, and developing automation scripts and AI/ML workflows to improve layout optimization, verification, modeling, quality metrics, and design efficiency. The position requires a technical bachelor's degree and at least 10 years of relevant experience, with analog layout, scripting, machine learning, CAD automation, and physical verification expertise preferred or required.

Required Skills

Analog layout
Scripting
AI/ML
PyTorch
Physical verification
Cadence Virtuoso
PCell creation

Additional Information

Minimum Education: Bachelor of Science degree in a technical discipline
Required Previous Experiences: At least 10 years of relevant experience
Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies
Strong programming and scripting skills in SKILL, Perl, TCL, Shell, and/or Python for layout automation, productivity tooling, and data analysis
Understanding of supervised and self-supervised learning, CNNs, loss functions, backpropagation, and optimization
Hands-on PyTorch experience for model development and experimentation
Ability to automate layout tasks, flows, and quality checks using scripting and CAD tools
Experience implementing high-quality analog layouts with tight device matching, low noise, and low power consumption
Familiarity with failure-prone circuit and layout structures, analog and DFM best practices, and layout issue diagnosis
Proficiency in custom and standard-cell floor planning, hierarchical layout assembly, and physical integration
Understanding of image processing, spatial representations, multi-channel image handling, segmentation, and object detection
Understanding of IR drop, RC delay, electromigration, self-heating, coupling capacitance, and reliability concerns
Proficiency interpreting DRC, ERC, and LVS physical verification reports
Experience with advanced Cadence Virtuoso features and familiarity with Cadence Innovus
Experience with CAD automation workflows and PCell creation
Excellent communication and cross-functional collaboration skills

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