Description
The Analog Layout Design Engineer will lead FPGA physical design and layout of complex digital, analog, and mixed-signal integrated circuits. Responsibilities include floorplanning, placement, routing, physical verification, design reviews, foundry compliance, documentation, and mentoring junior engineers. The role requires a bachelor’s or master’s degree in electrical engineering, microelectronics, or a related field, at least 8 years of analog/mixed-signal IC layout experience, and expertise with Cadence Virtuoso or Mentor Graphics. The position is regular employment in Shift 1 at Penang 15, Penang, Malaysia.
