Application Engineering, Principal Engineer at Synopsys

Location: Hyderabad, Telangana
Level: senior
Posted: Aug 31, 2026

Description

Synopsys is hiring a Physical Design Specialist (PDS) to support the sale and adoption of its semiconductor design products by helping customers improve cost, quality, and development time. The role focuses on advanced ASIC physical design, RTL-to-GDSII flows, back-end synthesis, placement, routing, clock-tree synthesis, timing closure, and advanced-node methodologies, while also supporting product demonstrations, evaluations, training, problem resolution, and technical account management. Candidates need strong ASIC design and Synopsys back-end tool experience, advanced-node design methodology knowledge, and excellent communication skills; BSEE or equivalent with 10+ years of experience, or MSEE or equivalent with 7+ years of experience, is preferred.

Required Skills

Place & Route
Logical Synthesis
Static Timing Analysis
Clock Tree Synthesis
Routing
RTL Coding
Equivalency Check
Timing Signoff
Fusion Compiler
ICC2
Innovus
Primetime

Additional Information

Required Previous Experiences: ASIC design experience using industry-standard placement, optimization, CTS, and routing tools
In-depth Synopsys back-end tool experience covering logical and physical synthesis, AI methodologies, timing closure, macro placement, routing, and static timing analysis
Understanding of advanced-node design methodologies
Preferred Qualifications: RTL-to-GDSII full-flow experience or knowledge
Knowledge of H-Tree and MS-CTS clock-tree synthesis methodologies
BSEE or equivalent with 10+ years of experience, or MSEE or equivalent with 7+ years of experience
Back-end P&R tool knowledge including Fusion Compiler, ICC2, and Innovus
Front-end synthesis tool knowledge including Fusion Compiler, Design Compiler, and Genus
STA tool knowledge including Primetime and Tempus