Description
Synopsys is hiring a Physical Verification Engineer to develop and validate DRC, LVS, Fill, ERC, and DFM rule decks for advanced semiconductor process nodes, including FinFET, GAA, and sub-3nm technologies. The role partners with foundries and customers, debugs layout verification failures, builds Perl, Tcl, and Python automation frameworks, and uses IC Validator, Calibre, or Pegasus to optimize production verification workflows. Candidates need a bachelor’s or master’s degree in a relevant technical field and at least five years of physical verification or semiconductor layout verification experience.
