Description
Synopsys is hiring a Physical Verification Engineer to develop and validate DRC, LVS, and Fill runsets for IC Validator across advanced semiconductor process nodes from 7nm to 3nm and beyond. The role works with foundries and customers to translate process design kits into production-ready rule decks, automates verification workflows with Perl, Tcl, and Python, debugs complex layout verification failures, supports customer escalations, mentors junior engineers, and tracks competitive EDA tools. Candidates need a B.Tech, M.Tech, or MS in electronics, VLSI, or a related discipline, 5-8 years of physical verification experience, and strong IC Validator, scripting, and CMOS design knowledge.
