Description
Synopsys is hiring an Application Engineer to support customers in digital design verification for chip development. The role combines technical verification work with customer-facing and pre-sales activities, including evaluations, demos, benchmarking, testbench architecture improvements, RTL and gate-level debugging, SystemVerilog/UVM environment support, coverage analysis, and assertion development. It is an individual-contributor role based in Theale, requiring 8–13 years of relevant experience, strong Verilog/SystemVerilog, UVM, coverage, and assertion knowledge, a bachelor’s degree in a relevant engineering field, and flexibility to travel to customer sites.
