Description
Synopsys is hiring a Senior Staff Formal Verification Applications Engineer to deploy and optimize VC Formal at semiconductor customer sites. The role involves diagnosing formal verification failures, integrating formal into customer flows, debugging tool performance, optimizing assertions and testbenches, delivering technical training, and translating customer requirements into product improvements. It requires a bachelor's or master's degree in a relevant engineering or computer science field, at least six years of formal verification experience, and strong expertise with formal verification tools, SystemVerilog Assertions, and semiconductor verification methodologies.
