Applications Engineering, Staff Engineer - 18837 at Synopsys

Location: Bengaluru, Karnataka
Type: Full-time
Level: senior
Posted: Sep 15, 2026

Description

Synopsys is hiring a Constraints Verification Applications Engineer in Bengaluru to partner with semiconductor customers and resolve end-to-end constraint-flow challenges, including SDC generation, verification, management, and signoff. The role deploys and optimizes Synopsys constraint tools, debugs timing and constraint issues, develops methodologies and automation, and collaborates with R&D, product validation, and account teams. Candidates need a BE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics, at least five years of ASIC design or verification experience, and strong knowledge of SDC, constraint methodologies, RTL, ASIC flows, STA, and scripting languages.

Required Skills

SDC generation
Constraint verification
Multi-modal analysis
VHDL
Verilog
SystemVerilog
TCL
Unix shell
Perl
Python

Additional Information

Minimum Education: BE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics
Required Previous Experiences: 5+ years of hands-on industry experience in ASIC design or verification
End-to-end SDC and constraint-flow experience, including generation, verification, management, and signoff
Experience with Synopsys constraint tools or equivalent industry-standard constraint verification and signoff tools
Strong RTL and ASIC design-flow experience with VHDL, Verilog, and SystemVerilog
Experience with timing closure, static timing analysis, and constraint-report debugging
Advanced scripting experience in TCL, Unix shell, Perl, or Python for automation and debugging