Description
Synopsys is hiring a VC Formal Staff Application Engineer in Bengaluru to lead the deployment of VC Formal at customer sites. The role assesses semiconductor verification environments, recommends formal methodologies, analyzes design blocks, diagnoses tool performance and proof-convergence issues, optimizes testbench modeling, delivers formal verification training, and communicates customer priorities to R&D. The position requires 4–8 years of hands-on formal verification experience in semiconductor design or verification, including formal property checking, sequential equivalence checking, formal coverage analysis, connectivity checking, and testbench optimization.
