Description
Synopsys is hiring a formal verification engineer to develop and maintain assertion IP for complex bus and memory protocols, create differentiating formal verification methodologies, validate Synopsys VC Formal and related EDA tool features, and collaborate with R&D, application engineers, and product management. The role requires a bachelor's or master's degree in a relevant discipline, 2–14 years of formal verification or EDA tool validation experience, hands-on VC Formal experience, synthesizable SystemVerilog assertion development, and scripting proficiency in Python, Perl, or Tcl within Unix/Linux environments.
