Description
Synopsys is hiring a Digital IC Design for Test Engineer to provide DFT expertise during design planning, RTL coding, tape-out readiness, and customer design reviews. The role covers scan compression, core wrapping, MBIST, ATPG, diagnostics, and the deployment and tuning of agentic AI flows for DFT. It requires a BSc with 7+ years or an MSc with 5+ years of relevant experience, strong RTL and DFT knowledge, silicon bring-up expertise, protocol knowledge, and practical fluency with LLM-based coding assistants and agentic tools.
