Applications Engineering, Staff Engineer DFT at Synopsys

Synopsys is hiring a Digital IC Design for Test Engineer to provide DFT expertise during design planning, RTL coding, tape-out readiness, and silicon bring-up. The role involves scan compression, core wrapping, logic and memory BIST, ATPG, test methodology validation, diagnostics, customer design reviews, and technical support. Candidates need a BSc with 7+ years or an MSc with 5+ years of relevant experience, along with RTL, DFT insertion, scan synthesis, ATPG, MBIST, pattern generation, and silicon bring-up expertise, plus knowledge of 1149.x, 1500, and 1687 protocols.