ASIC & FPGA Design Engineer Stf - E4 (FULLTIME TELEWORK) at Lockheed Martin

Department: RMS Core

Compensation

$150,800 – $280,000/yr

Setup: Remote
Location: Owego, New York
Type: Full-time
Level: senior
Posted: Sep 22, 2026

Description

Lockheed Martin is hiring an experienced FPGA Designer for its Mission Systems team in Owego, New York. The role supports advanced processing systems and subsystems from requirements through product integration, including FPGA development, technical guidance, process compliance, deliverable quality, customer coordination, and digital transformation. The position requires a relevant bachelor’s or master’s degree, approximately seven to nine years of experience, significant FPGA design and verification experience, proficiency with FPGA development tools, and the ability to obtain and maintain a Secret-level DoD clearance. The role offers a hybrid telework option and a full-time salary range of $150,800 to $280,000 in the listed geographic zone.

Required Skills

FPGA architecture
RTL design
VHDL
Verilog
SystemVerilog
Vivado
Quartus
Libero
DO-254
Timing analysis
UVM
Python
Git
CI/CD

Additional Information

Minimum Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent experience; a master’s degree is also accepted with approximately seven or more years of experience.
Required Previous Experiences: Approximately nine or more years of relevant experience for a bachelor’s degree holder.
Approximately seven or more years of experience for a master’s degree holder.
Significant FPGA architecture, RTL design, implementation, integration, and verification experience using VHDL, Verilog, or SystemVerilog.
Hands-on experience in hardware design and system engineering, particularly with advanced processing systems.
Preferred Qualifications: DO-254 design assurance, traceability, coverage, audits, or certification evidence.
AMD/Xilinx FPGA/SoC/ACAP, PolarFire/PolarFire SoC, or Intel FPGA experience.
PCIe, Ethernet, DDR, JESD204, Aurora, SERDES, LVDS, AXI, or source-synchronous interfaces.
Advanced timing analysis, CDC/RDC, floorplanning, pin/bank validation, and timing closure.
UVM, constrained-random verification, coverage, regression automation, formal methods, or HIL.
Python, Tcl, MATLAB, C/C++, or similar automation skills.
Git, CI/CD, automated builds/regressions, issue tracking, and configuration management.
FPGA technical-review leadership and multidisciplinary/customer coordination.
Estimates, schedules, staffing plans, technical risks, and program-leadership status.
Mentoring, knowledge transfer, reuse, and process-improvement experience.