Description
NVIDIA is hiring an ASIC STA Engineer for its Networking Silicon engineering team to develop high-speed communication devices for AI platforms. The role owns full-chip and/or chiplet-level STA convergence from early stages through signoff, contributes to floor planning and clock planning, optimizes CAD signoff flows, integrates digital and analog IP timing, and collaborates with logic design and DFT engineers on constraints and runtime efficiency. Candidates need an electrical or computer engineering degree, at least three years of physical design and STA experience, RTL-to-GDS and STA convergence experience, familiarity with Synopsys or Cadence tools, and hands-on Primetime STA experience from early stages through signoff.
