Description
Annapurna Labs is hiring an ASIC Design Engineer to lead and grow a team of SOC integration engineers responsible for critical deliverables in machine-learning accelerator chips. The role drives technical decisions across RTL, timing, DFT, and physical design; ensures complex SOC integration milestones are delivered; establishes clock/reset, CDC, and quality-metrics practices; and coordinates with architecture, verification, and physical design teams. Candidates need at least 10 years of equivalent experience, 3+ years of people management experience, SOC integration expertise, and a track record of successful tape-outs in leading-edge nodes. The position is based in Cupertino, California, or Austin, Texas, with annual base salaries of $239,600–$324,100 USD in Cupertino and $208,300–$281,800 USD in Austin.
