Description
Axiado is hiring an ASIC/SoC Design Engineer to develop and implement smart-edge SoCs for network, systems control, management, security, and IIoT applications. The role covers micro-architecture design, RTL coding, synthesis, timing closure, performance and power optimization, FPGA prototyping, test-program development, chip validation, and collaboration with architecture, verification, physical design, software, firmware, DFT, and backend teams. The position requires 8+ years of RTL design and verification experience, expertise in Verilog and SoC integration, knowledge of interface protocols, FPGA emulation, scripting, and at least one tapeout.
