ASIC Design Engineer at Google

Seniority in posting: Mid

Compensation

$138,000 – $197,000/yr

Location: Mountain View, California
Type: Full-time
Level: mid
Posted: Aug 13, 2026

Description

Google is hiring an ASIC Design Engineer to define microarchitecture, integrate and develop internal and external IP, perform RTL coding and simulation debugging, and participate in chip-level verification. The role requires a bachelor's degree in a relevant engineering or computer science field, four years of IP development or integration experience, ASIC development experience with Verilog or VHDL, and scripting experience with Perl or Python. Preferred qualifications include advanced degrees, ASIC design methodologies, processor and bus knowledge, FPGA and emulation experience, and ASIC verification or DFT knowledge. The position offers $138,000–$197,000 USD plus a 15% bonus target, equity, and benefits, and typically requires in-person interviews.

Required Skills

Microarchitecture
RTL coding
Verilog
VHDL
Python
Chip verification

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
Required Previous Experiences: 4 years of IP development or integration experience
ASIC development experience with Verilog or VHDL
Scripting experience with Perl or Python
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture
ASIC design methodologies for clock domain checks, reset checks, and low-power design
Knowledge of processor cores, buses, NoC, debug, interrupts, or clocks and resets
High-performance and energy-efficient design techniques
FPGA and emulation platform knowledge
ASIC verification or DFT knowledge