ASIC Design Engineer at Google

Seniority in posting: Advanced

Location: Bengaluru, Karnataka
Level: senior
Posted: Jul 20, 2026

Description

The role is an ASIC design engineer position in Google's Bengaluru design organization, focused on developing complex IP and subsystems for TPU and data-center accelerator technologies. Responsibilities include owning microarchitecture and implementation, collaborating with architecture, firmware, software, verification, and physical design teams, establishing design methodology and debug practices, and improving power, performance, and area. The position requires a bachelor's degree in a relevant engineering or computer science field and 10 years of ASIC development experience, along with experience in verification, synthesis, timing and power analysis, DFT, and networking-domain microarchitecture.

Required Skills

ASIC development
Verilog/SystemVerilog
ASIC verification
Microarchitecture
Timing analysis
DFT
Packet processing

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
Required Previous Experiences: 10 years of ASIC development experience with Verilog/SystemVerilog and VHDL
Experience in ASIC design verification, synthesis, timing and power analysis, and DFT
Experience in microarchitecture and design of networking-domain IP and subsystems
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture
Experience with Python, C/C++, or Perl
Experience in SoC design and integration flows
Knowledge of arithmetic units, processor design, accelerators, bus architectures, NoC, or memory hierarchies
Knowledge of high-performance and low-power design techniques