Hewlett Packard Enterprise is hiring an onsite ASIC Design Engineer to design and architect high-performance networking ASICs, perform micro-architecture and logic design, collaborate on verification test plans and debugging, and work with physical design on timing constraints and fixes. The role requires strong Verilog RTL coding, ASIC debugging, knowledge of high-performance memory and multi-domain clock synchronization, and an MSEE or BSEE with at least five years of experience.
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