Description
Apple is hiring a hardware engineer to design and develop cache subsystems for high-performance system-on-chip (SoC) memory hierarchies. The role involves developing cache micro-architecture, exploring performance, area, and power tradeoffs, creating and debugging register-transfer-level designs, working on front-end netlists and area/timing analysis, and collaborating with the physical design team on timing closure. The minimum qualifications include in-depth knowledge of memory subsystems, RTL and micro-architecture development experience, PPA tradeoff knowledge, and a bachelor's degree in a relevant field; a master's degree and cache or memory-system experience are preferred.
