Description
Apple is hiring an ASIC Cache Design Engineer to design and develop hardware for the cache subsystem of a high-performance system on a chip. The role involves defining cache micro-architecture, exploring performance, area, and power trade-offs, developing and debugging register-transfer-level designs, working on front-end netlists and area/timing analysis, and collaborating with the physical design team on timing closure. The position requires at least 10 years of full-time ASIC design experience, memory-system and cache-design expertise, multi-processor cache-coherence knowledge, and a relevant bachelor's degree.
