Description
The NVIDIA GPU clocks group is hiring a Senior ASIC Design Engineer to architect, design, and validate GPU clocking RTL, collaborate with frontend, backend, verification, timing, and DFT teams, and improve clock-flow productivity using Perl or Python. The role also involves debugging GPU clock silicon bugs and requires a BS or MS in electrical engineering or equivalent experience, at least two years of meaningful work experience, and validated RTL design, verification, and logic synthesis experience.
