ASIC Design Engineer — Pixel IP at Apple

Department: Hardware

Compensation · Listed in posting

$184,700 – $324,800

Location: Sunnyvale, California
Level: senior
Posted: Aug 28, 2026

Description

The ASIC Design Engineer will design high-performance, low-power pixel processing engines for Apple’s Pixel IP, creating digital signal processing pipelines for image and video capture, processing, compression, decompression, and display. The role involves RTL or high-level synthesis design, micro-architectural specifications, cross-functional collaboration, synthesis, power, timing, and area optimization, and verification with design and formal verification teams.

Required Skills

RTL design
Verilog
SystemVerilog
Low-power design
Synthesis
Timing analysis
Formal verification
AMBA

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering or Computer Engineering
Required Previous Experiences: 10+ years of relevant industry experience
Preferred Qualifications: Extensive SoC front-end ASIC RTL digital logic design experience using Verilog and SystemVerilog
Deep experience in media, video, pixel, or display designs
Experience with clock- and power-gating techniques
Cross-functional experience with architecture, design, and verification teams
Familiarity with AMBA bus protocols
Front-end implementation experience including synthesis, timing, area/power analysis, linting, CDC/RDC, and logic equivalence checks
ASIC design methodology and scripting language experience

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