ASIC Design Verification, Architect at Synopsys

Synopsys is hiring an experienced ASIC Digital Verification Architect to define and develop ASIC RTL design and verification at chip and block levels, create and execute verification plans for complex digital designs involving HBM or PCIe/CXL, collaborate with cross-functional teams, apply advanced verification methodologies and tools, mentor junior engineers, and communicate technical concepts to internal and external stakeholders. The role focuses on improving digital verification reliability, performance, and time-to-market while contributing to HBM or PCIe/CXL technology and semiconductor innovation.