Description
The ASIC Design Verification Engineer will verify next-generation custom silicon accelerators and SoCs, build constrained-random UVM test environments, and collaborate with design, architecture, and emulation teams. Responsibilities include creating verification plans, testbenches, test cases, coverage-driven plans, power-aware simulations, and formal verification. The role requires a bachelor's degree in a relevant engineering or computer science field or equivalent practical experience, plus one year of UVM verification experience at the IP or subsystem level.
