Qualcomm International Inc., Mexico Branch Office

ASIC Design Verification Engineer (Santa Clara, CA) at Qualcomm International Inc., Mexico Branch Office

Department: ASICS Engineering

Compensation

$134,500 – $201,700/yr

Setup: On-site
Location: California
Type: Full-time
Level: mid
Posted: Sep 17, 2026

Description

Qualcomm is hiring an ASIC Design Verification Engineer to own the complete verification lifecycle for digital power IP, from pre-silicon test planning through tapeout and post-silicon support. The role focuses on SystemVerilog-UVM testbench development, coverage and assertion modeling, formal verification, power-aware UPF verification, automation, and DDR, cache, and SOC verification. Candidates need substantial ASIC design verification experience, relevant academic credentials, and exposure to DDR, C++, Python, and related verification technologies. The listed pay range is $134,500 to $201,700.

Required Skills

SystemVerilog-UVM
Assertion
C++
Python
DDR
Cache
Formal verification
UPF verification

Additional Information

Minimum Education: Bachelor's degree in Science, Engineering, or a related field with at least 2 years of relevant ASIC design, verification, validation, integration, or related experience; alternatively, a master's degree with at least 1 year of relevant experience, or a PhD in Science, Engineering, or a related field.
Required Previous Experiences: At least 3 years of design verification experience using UVM and assertion-based verification technologies.
Experience verifying complex SOC or SOC subsystems.
Experience verifying cache and DDR memory protocols.
Experience using memory verification VIPs.
Exposure to DDR PHY.
Exposure to firmware and driver development using C++.
Exposure to multiple successful tapeouts from conception through post-silicon debug.
Exposure to formal verification.
Exposure to PASIM simulations.
Exposure to performance and power verification.