ASIC Design Verification Manager at Google

Google is hiring an ASIC Design Verification Manager to lead functional verification for TPU designs and guide verification infrastructure across subchip, subsystem, and full-chip levels. The role defines verification strategies, develops test plans, monitors, checkers, and diagnostic code, partners with design, architecture, and performance teams, and analyzes coverage to ensure architectural compliance and performance goals. Candidates need a bachelor's degree in a relevant engineering or computer science field, 10 years of verification, SystemVerilog, and UVM experience, and 3 years of people-management experience.