ASIC Design / Verification, Manager-Sr Manager at Synopsys

Language

Location: Hsinchu
Level: lead/mgmt
Posted: Sep 16, 2026

Description

The role leads the design and verification of Synopsys DesignWare IP cores and SoCs, including memory controllers and HBM IPs. Responsibilities include specifying and implementing RTL and UVM testbenches, leading engineering teams, coordinating with RTL designers and architects, debugging regressions, and ensuring product release milestones. The position requires a BS/MS in EE/EC/VLSI, 15+ years of relevant IP or SoC verification experience, strong Verilog/System Verilog and UVM skills, memory protocol knowledge, and proficiency with Perl or Python-based automation.

Required Skills

Verilog/System Verilog
UVM
RTL design
Memory protocols
Perl/Python automation

Additional Information

Minimum Education: BS/MS in Electrical Engineering, Electrical and Computer Engineering, or VLSI
Required Previous Experiences: 15+ years of relevant IP core and/or SoC verification experience
Experience leading a team of engineers and guiding them toward project milestones
Hands-on RTL design and/or verification of complex IP or SoC designs
Experience developing testbenches in UVM environments
Experience with HBM, DDR, and LPDDR memory protocols and IP design and verification tools
Proficiency in Perl or Python-based automation and strong communication and problem-solving skills